Phase-Locked Loop Circuit Design Dan H. Wolaver
Publisher: Prentice Hall

Evaluating VCO performance is the first step toward designing a better. (Bias-tee circuit) about 1~3 mVrms or less bypass capacitor. Behzad Razavi 's collection of IEEE papers about monolithic PLL and CDR circuits. This is an integrated vco/pll so it is a chip. The second step is to design the optimal loop filter for lower phase/spurious noise and faster frequency transient response. I am trying to teach myself about PLL, and I am trying to start by building a known design. What more i must buy to make this one a device with port to feed my mixer. Design of Monolithic Phase-Locked Loopsand Clock Recovery Circuits-A TutorialBehzad RazaviAbstract - This paper describes the principles of phase-locked system design with emphasis on monolithic imple-mentations. In practice some frequency conversion is required, this could be a frequency multiplier based on a PLL or a frequency divider. (50 Hz ~ 1 MHz) to Baseband input. This is the simple electronic siren schematic, built using three ICs: CD4011 NAND gate logic, CD4066 Bilateral Switch and CD4046 Micro power Phase-Locked Loop (PLL). So I decided to build a PLL using the 74HC4046 chip from NXP. Often both need to be used in a practical circuit. Http://www.nxp.com/documents/data_shT4046A_CNV.pdf. The phase locked loop circuits are essential parts especially for frequency modulation and demodulation in System on Chip (SoC) integratedcircuits. I asked mini-circuits and proposed me this: http://pdf1.alldatasheet.com/datashe2554A-119.html.